1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems including hardware accelerators and the interface used to couple such hardware accelerators to the remainder of the data processing system.
2. Description of the Prior Art
It is known to provide hardware accelerators of various different forms in order to increase the performance and efficiency of data processing systems. One type of hardware accelerator are large bus-based accelerators, such as video accelerators. These accelerators are usually accessed through device driver software and carry a high overhead for initiating tasks to be accelerated. Accordingly the tasks to be accelerated have to be large in order to effectively amortise this setup cost. Furthermore, the use of the device driver requires the involvement of the operating system and modification thereof, which is a disadvantage.
Another type of known hardware accelerator are coprocessors, such as the coprocessors known in conjunction with ARM general purpose processors. With such coprocessors, the general purpose processor is responsible for supplying both instructions and data to the coprocessor. This disadvantageously consumes resource of the general purpose processor thereby reducing the gain achieved. Furthermore, in order to lower the overhead associated with invoking the coprocessor activity, the coprocessor interface to the general purpose processor is closely adapted to the underlying micro-architecture of the general purpose processor. This makes it difficult to reuse coprocessor designs across multiple different general purpose processors.
It is also known to provide core extensions to the configurable processors produced by companies such as ARC and Tensilica. These configurable processors provide a mechanism for mapping hardware assistance into the instruction set of the main core. This provides access to the registers of the core by the hardware assist circuitry and may also add new registers to the core if appropriate. However, this approach requires changes to the assembler and compiler software for the core in order to support new added instructions. Such modification of the software tool chain is time consuming and expensive. Furthermore, load and store traffic to the hardware assist circuitry is normally handled by the core load-store instructions consuming resource of the general purpose processor. Some examples using FIFO interfaces to the hardware assist circuitry are known but these use a DMA unit to load them and do not integrate with the memory management functions of the system as a whole.